In a NAND flash memory, out of a plurality of memory cells arranged in rows and columns, half cells arranged in rows undergo a write or read operation. More specifically, the plurality of cells arranged in columns are connected to even-numbered bit lines BLe or odd-numbered bit lines BLo. In the data write or read mode, one of a pair of bit lines BLe and BLo is connected to a sense amplifier SA via a pair of first bit line select transistors. A signal BLSe or BLSo is supplied to the gate electrodes of these first bit line select transistors. A predetermined BL voltage is applied to an unselected bit line of the pair of bit lines BLe and BLo. For this purpose, a pair of second bit line select transistors are connected to bit lines BLe and BLo. A signal BIASe or BIASo is supplied to the gate electrodes of these second bit line select transistors. One of the second bit line select transistors is selected by signal BIASe or BIASo.
The first and second bit line select transistors are arranged on a p-type substrate (Psub). The memory cell array is provided in a p-type well region (CPWELL) for memory cells, which is formed in an n-type well region (NWELL) formed in the Psub.
In the erase mode of the NAND flash memory, Pusb=0V, and NWELL=CPWELL=Vera (erase voltage: for example, 20V) are set, and a plurality of word lines WL included in an erase target block are set to 0V. When the CPWELL is set to Vera, a cell source line CELSRC and the bit lines are forward biased. Hence, the cell source line CELSRC and the bit lines are also set to Vera. The first and second bit line select transistors are provided on the Psub (0V). For this reason, when the bit lines are set to Vera, the voltage Vera is applied to the first and second bit line select transistors as well. It is therefore necessary to form the first and second bit line select transistors using high-voltage transistors. However, the high-voltage transistors have a long channel or large diffusion layer, resulting in a large chip size.
Along with the progress of micropatterning, the pitches between interconnects such as bit lines become narrower. One of the two bit lines BLe and BLo is selected and connected to a sense amplifier bit line SABL. Bit line SABL is connected to the sense amplifier. Since the sense amplifier is formed from a low-voltage transistor, the voltage of bit line SABL needs to be Vdd (2.5V) or less. The first and second bit line select transistors form an interconnect structure in which the bit lines to which Vera is applied are close to bit line SABL to which a voltage less than or equal to Vdd is applied. In such an interconnect structure, as the elements become smaller, it becomes more difficult to hold the breakdown voltage between the interconnects.
A technique of arranging first and second bit line select transistors in a CPWELL has been disclosed (for example, Jpn. Pat. Appln. KOKAI Publication No. 8-46159). In this arrangement, the first and second bit line select transistors are formed in a CPWELL, and can therefore be formed from low-voltage transistors. In this case, however, the first bit line select transistors are arranged on the sense amplifier side with respect to the memory cell array, whereas the second bit line select transistors are arranged on the side opposite to the sense amplifier with respect to the memory cell array. For this reason, a voltage generation circuit for generating a power to drive the second bit line select transistors also needs to be arranged on the side opposite to the sense amplifier with respect to the memory cell array. A power pad is generally arranged on the sense amplifier side. Hence, the interconnect that connects the power pad to the voltage generation circuit is long, resulting in a large chip size.
The read operation of the NAND flash memory will briefly be explained. When bit line BLe is selected out of the pair of bit lines BLe and BLo, signal BLSe supplied to the gate electrode of the first bit line select transistor that selects the bit line goes high, and signal BLSo goes low. Bit line BLe is then connected to the sense amplifier via the first bit line select transistor. In addition, signal BIASo goes high, and signal BIASe goes low so that the second bit line select transistor sets a potential BLCRL in the unselected bit line BLo. Bit lines BLe and BLo are arranged in parallel. For this reason, when bit line BLe is selected, the adjacent bit line BLo is set to the potential BLCRL to serve as a shield for bit line BLe. More specifically, since a cell current flows to the selected bit line BLe because of the threshold voltage of the cell, the potential of bit line BLe is fluctuated. The potential change of bit line BLe does not influence other bit lines BLe. Hence, when bit line BLo serves as a shield, the read margin improves.
The cell current flows to bit line BLe, and then flows into the cell source line CELSRC. When the cell current flows to bit line BLe, the potential of bit line BLe falls. Because of capacitive coupling, the potential of bit line BLo also falls. The potential of bit line BLo is BLCRL. If the voltage generation circuit for generating BLCRL is far from the power pad, the interconnect resistance between the power pad and the voltage generation circuit increases to make it impossible to generate the necessary potential BLCRL. Hence, the shielding effect becomes poor, and the read margin decreases. To prevent this, a semiconductor memory device capable of suppressing an increase in the chip size and preventing a decrease in the read margin is demanded.